Bangalore: Tektronix, Inc., a leading worldwide provider of test, measurement and monitoring instrumentation, today announced availability of a complete DDR2 protocol debug and validation solution for the award-winning TLA6000 Series Logic Analyzers. The new options for the TLA6000 Series consist of everything embedded engineers – even those who are not DDR2 experts – need to validate and debug the operation of memory sub-systems in their designs.

DDR2 memory systems are used in many of today’s embedded designs – commonly implemented as a bus on the microprocessor or as a block in an FPGA. The complexity of the DDR2 protocol and the number of command/data/address signals make it difficult to both visualize the operation of the bus and to isolate any potential problems. In addition, designers need to ensure that signal timing and interfaces comply with JEDEC standards. The new DDR2 options for the TLA6000 Series meet the emerging need for a more complete, easier to user DDR2 test solution at a more affordable price point.

“These options will significantly boost productivity for engineers tasked with validation and debug of DDR2 in embedded designs while lowering costs by bringing these capabilities to our mid-range logic analyzers,” said Dave Farrell, director, Logic Analyzer Product Line, Tektronix. “Users don’t need to be a DDR2 expert to get expert-level results since the included software translates the raw captured data into meaningful DDR2 bus transaction views, and finds and reports protocol violations automatically.”

The new options for the TLA6000 Series consists of a set of tools designed to provide visibility to all address, data, and control signals. The bundle includes:

• Memory chip interposers that provide a convenient way of probing embedded DDR memory systems and eliminates the need to design in probe access points. These memory chip interposers work with the unique iCapture Analog Mux feature of the TLA6000 to provide a single probing solution for both the logic analyzer and oscilloscope, saving time and minimizing setup complexity.
• Protocol decode software that shows all of the DDR2 transactions as well as providing triggering on DDR2 events.
• Sample point analysis software that automates the process of correctly configuring the TLA6000 Series to accurately sample the DDR2 signals.
• Protocol violation software that finds and reports any violation of the JEDEC-defined DDR2 protocol.

“This DDR2 solution provides fast and smart analysis capabilities for debug and validation engineers. When coupled with Tektronix logic analyzers’ deep memory, powerful triggering, and cross-bus correlation capabilities, these new options for the TLA6000 give engineers the best tools in the industry for embedded memory debug and validation,” said Rob Shelsky, President, Nexus Technology, Inc.

Availability

The new DDR2 option for the TLA6000 Series will be available globally beginning April 2011.