Synopsys, Inc. , a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced that Achronix Semiconductor has successfully used both Synopsys’ IC Compiler™ physical design and IC Validator physical verification solutions to signoff its Speedster22i® FPGA–the industry’s first system-on-chip (SoC) design using finFET transistors. Enabled by finFETtechnology, Achronix’s Speedster22i promises significant power, performance and cost benefits relative to competitive offerings. Synopsys’ IC Compiler physical implementation tool has been enhanced to support correct-by-construction implementation of all finFET-specific design rules,while the IC Validator physical verification tool used foundry rule decks to enable fast, accurate verification of finFET-based SoCs and extraction of new finFET device parameters. IC Compiler and IC Validator are now the standard solutions for place-and-route, design-rule-checking (DRC), and layout-vs.-schematic (LVS) checking in Achronix’s design flow.

“Our experience with a 22-nanometer test chip impressed us with Synopsys’ ability to handle the complex technology requirements demanded by our finFET-based process,” said Rahul Nimaiyar, vice president of hardware engineering at Achronix. “The quality of layout results as well as the excellent multi-CPU scalability of DRC and the high productivity of LVS debug make Synopsys the best physical implementationsolution on the market for finFETdesigns.”

Synopsys’ FinFET-ready Design Tools

Conventional approaches to continually shrink the conductive channel length of flat or planar transistors are facing serious limitations. In order to achieve acceptable switching performance, shorter conductive channel lengths tend to place additional burden on power and voltage.FinFET technology features non-planar (3D) transistor channels that wrap around a raised silicon “fin.”FinFETs can be driven by a lower supply voltage and can switch transistors off completely, thereby reducing leakage and dynamic power consumption. Additionally, finFETs can be switched on and off more rapidly, which increases maximum IC performance.

The shift from planar to finFET-based 3D transistors is a significant change that requires close technical collaboration between tool developers, foundries and early adopters to deliver a strong solution. Synopsys’finFET-ready IC Compiler physical design tool provides complete coverage for advanced routing rules and double patterning requirements. IC Validatorhas been enhanced to support all new finFET-specific DRC checks, such as fin-to-fin spacing and fin-width.It can also extract new device parameters, such as the fin gate’s series resistance and the impact of neighboring layout structures of a finFET’s electrical parameters.

“Having been successfully applied in early production designs using finFET technology, IC Compiler and IC Validator are uniquely positioned as the silicon manufacturing industry moves to finFET technology,” said Antun Domic, senior vice president and general manager of Synopsys’ Implementation Group. “We will continue to work with Achronix and other leading customers and foundries to maintain the demonstrated advantages of Synopsys in both design and verification applications.”